6502DecimalMode

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(add some BCD tests, add linkage and minor rewording)
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Decimal mode only affects ADC and SBC instructions, and on the NMOS 6502 only usefully sets the C flag. The N, V and Z flags are set, but don't correspond to what you might expect from a 10's complement decimal operation.
Decimal mode only affects ADC and SBC instructions, and on the NMOS 6502 only usefully sets the C flag. The N, V and Z flags are set, but don't correspond to what you might expect from a 10's complement decimal operation.
-
Nonetheless, all four flags are set, so it's worth understanding how they are set, and why. (Link to Ijor's paper, and Bruce's tutorial)
+
Nonetheless, all four flags are set, so it's worth understanding how they are set, and why. (See [http://www.atariage.com/forums/topic/163876-flags-on-decimal-mode-on-the-nmos-6502 Ijor's paper], and [http://www.6502.org/tutorials/decimal_mode.html Bruce Clark's tutorial])
-
Many (software) emulators have decimal mode correct, and many have it incorrect or missing. Because the CMOS 6502 and later parts set the flags differently, correctness can only be judged relative to a specific part.
+
Many (software) emulators have decimal mode correct, and many have it incorrect or missing. The same is true for [http://forum.6502.org/viewtopic.php?t=1673 various re-implemented 6502 cores]. Because the CMOS 6502 and later parts set the flags differently from the NMOS 6502, correctness can only be judged relative to a specific part.
-
We need some test cases - these may yet be added to the py65 test suite (link), once they have been validated against the transistor-level simulation.  At the time of writing, py65 will fail some of these tests, but perhaps not for long.
+
We need some test cases - some of these are now found in the [https://github.com/mnaberez/py65/tree/master/src/py65/tests/devices py65 test suite]
Need a list of interesting signals to probe to observe the decimal mode adjustments. (The presently released JSSim doesn't have C34 named, but it will on next update)
Need a list of interesting signals to probe to observe the decimal mode adjustments. (The presently released JSSim doesn't have C34 named, but it will on next update)
-
The two operands, and the carry in, are added as a pair of nibbles. The carry-out from bit3 is adjusted in decimal mode, only for ADC. So the ALU is not a binary byte-wide ALU with a decimal adjustment, it is a pair of binary nibble ALUs with a decimal adjustment.  In the tests, we don't specifically need to test that carry-in is used (except to prove that carry-out is changing the carry bit, if we have that freedom)
+
The two operands, and the carry in, are added as a pair of nibbles. The carry-out from bit3 is adjusted in decimal mode, but only for ADC. So the ALU is not a binary byte-wide ALU with a decimal adjustment, it is a pair of binary nibble ALUs with a decimal adjustment.  In the tests, we don't specifically need to test that carry-in is used (except to prove that carry-out is changing the carry bit, if we have that freedom)
-
Some of the tests below are found in Bruce Clark's [http://www.6502.org/tutorials/vflag.html#b V flag tutorial].
+
Some of the tests below are found in Bruce Clark's [http://www.6502.org/tutorials/vflag.html#b V flag tutorial]. Others are taken from failing cases when running his [http://www.6502.org/tutorials/decimal_mode.html#B decimal mode test suite].
=== Tests for ADC ===
=== Tests for ADC ===
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* 80 + fa and C=0 gives e0 and N=1 V=0 Z=0 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a97e48a9802869faea08aa6849c2ea simulate])
* 80 + fa and C=0 gives e0 and N=1 V=0 Z=0 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a97e48a9802869faea08aa6849c2ea simulate])
* 2f + 4f and C=0 gives 74 and N=0 V=0 Z=0 C=0 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9fe48a92f28694fea08aa6849c2ea simulate])
* 2f + 4f and C=0 gives 74 and N=0 V=0 Z=0 C=0 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9fe48a92f28694fea08aa6849c2ea simulate])
 +
* 6f + 00 and C=1 gives 76 and N=0 V=0 Z=0 C=0 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9ff48a96f286900ea08aa6849c2ea simulate])
=== Tests for SBC ===
=== Tests for SBC ===
* 00 - 00 and C=0 gives 99 and N=1 V=0 Z=0 C=0 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a94e48a90028e900ea08aa6849c2ea simulate])
* 00 - 00 and C=0 gives 99 and N=1 V=0 Z=0 C=0 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a94e48a90028e900ea08aa6849c2ea simulate])
* 00 - 00 and C=1 gives 00 and N=0 V=0 Z=1 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9c948a90028e900ea08aa6849c2ea simulate])
* 00 - 00 and C=1 gives 00 and N=0 V=0 Z=1 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9c948a90028e900ea08aa6849c2ea simulate])
 +
* 00 - 01 and C=1 gives 99 and N=1 V=0 Z=0 C=0 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a97f48a90028e901ea08aa6849c2ea simulate])
* 0a - 00 and C=1 gives 0a and N=0 V=0 Z=0 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9cb48a90a28e900ea08aa6849c2ea simulate])
* 0a - 00 and C=1 gives 0a and N=0 V=0 Z=0 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9cb48a90a28e900ea08aa6849c2ea simulate])
* 0b - 00 and C=0 gives 0a and N=0 V=0 Z=0 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9ca48a90b28e900ea08aa6849c2ea simulate])
* 0b - 00 and C=0 gives 0a and N=0 V=0 Z=0 C=1 ([http://visual6502.org/JSSim/expert.html?graphics=f&steps=56&a=0&d=a9ca48a90b28e900ea08aa6849c2ea simulate])
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  php
  php
  pla
  pla
-
  EOR #$c3  // #$c2 if we don't want to invert the carry
+
  eor #$c3  // #$c2 if we don't want to invert the carry
  nop
  nop

Revision as of 20:31, 15 December 2010

The 6502 had a couple of unique selling points compared to its predecessor the 6800, and the decimal mode was crucial because it was patent protected. It saves an instruction and a couple of cycles from each byte of decimal arithmetic, and removes the half-carry from the status byte - it also works for both addition and subtraction.

Decimal mode only affects ADC and SBC instructions, and on the NMOS 6502 only usefully sets the C flag. The N, V and Z flags are set, but don't correspond to what you might expect from a 10's complement decimal operation.

Nonetheless, all four flags are set, so it's worth understanding how they are set, and why. (See Ijor's paper, and Bruce Clark's tutorial)

Many (software) emulators have decimal mode correct, and many have it incorrect or missing. The same is true for various re-implemented 6502 cores. Because the CMOS 6502 and later parts set the flags differently from the NMOS 6502, correctness can only be judged relative to a specific part.

We need some test cases - some of these are now found in the py65 test suite

Need a list of interesting signals to probe to observe the decimal mode adjustments. (The presently released JSSim doesn't have C34 named, but it will on next update)

The two operands, and the carry in, are added as a pair of nibbles. The carry-out from bit3 is adjusted in decimal mode, but only for ADC. So the ALU is not a binary byte-wide ALU with a decimal adjustment, it is a pair of binary nibble ALUs with a decimal adjustment. In the tests, we don't specifically need to test that carry-in is used (except to prove that carry-out is changing the carry bit, if we have that freedom)

Some of the tests below are found in Bruce Clark's V flag tutorial. Others are taken from failing cases when running his decimal mode test suite.

Tests for ADC

  • 00 + 00 and C=0 gives 00 and N=0 V=0 Z=1 C=0 (simulate)
  • 79 + 00 and C=1 gives 80 and N=1 V=1 Z=0 C=0 (simulate)
  • 24 + 56 and C=0 gives 80 and N=1 V=1 Z=0 C=0 (simulate)
  • 93 + 82 and C=0 gives 75 and N=0 V=1 Z=0 C=1 (simulate)
  • 89 + 76 and C=0 gives 55 and N=0 V=0 Z=0 C=1 (simulate)
  • 89 + 76 and C=1 gives 56 and N=0 V=0 Z=1 C=1 (simulate)
  • 80 + f0 and C=0 gives d0 and N=0 V=1 Z=0 C=1 (simulate)
  • 80 + fa and C=0 gives e0 and N=1 V=0 Z=0 C=1 (simulate)
  • 2f + 4f and C=0 gives 74 and N=0 V=0 Z=0 C=0 (simulate)
  • 6f + 00 and C=1 gives 76 and N=0 V=0 Z=0 C=0 (simulate)

Tests for SBC

  • 00 - 00 and C=0 gives 99 and N=1 V=0 Z=0 C=0 (simulate)
  • 00 - 00 and C=1 gives 00 and N=0 V=0 Z=1 C=1 (simulate)
  • 00 - 01 and C=1 gives 99 and N=1 V=0 Z=0 C=0 (simulate)
  • 0a - 00 and C=1 gives 0a and N=0 V=0 Z=0 C=1 (simulate)
  • 0b - 00 and C=0 gives 0a and N=0 V=0 Z=0 C=1 (simulate)
  • 9a - 00 and C=1 gives 9a and N=1 V=0 Z=0 C=1 (simulate)
  • 9b - 00 and C=0 gives 9a and N=1 V=0 Z=0 C=1 (simulate)

One form of test program sets all the input flags using PLP:

lda #$c8
pha
lda #$00
plp
adc #$00
nop

and to calculate what that initial value of PLP should be, we can use a bit more code

php
pla
eor #$c3   // #$c2 if we don't want to invert the carry
nop
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