6502 Opcode 8B (XAA, ANE)

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Of all the unsupported opcodes, 8B has had a lot of attention because it seems unpredictable. Even the same computer has been seen to act differently even with the same inputs.

The reason is that this opcode connects the A register to SB (the Special Bus) at both input and output: in a sense, A is both read and written. Unlike the stack pointer, the A register is not designed to do that, and the result is a circuit configuration which behaves in an interesting way.

Note that our switch-level simulation tends to produce wired-AND behaviour: if two logic gates both drive the same wire, then either of them can drive it low. A real 6502 usually does the same, which is why 8B - often called XAA - will more or less AND together the three inputs: the X register, the A register, and the immediate operand.

Why more or less? Two reasons: the A register is fed back on itself, and because of an interaction with the RDY input.

The A register drives the SB directly, and bits 0 and 4 read SB directly. The other 6 bits read SB through the Decimal Adjust logic, which doesn't affect the logic value but does affect the timing, the logic thresholds and the drive strengths. Exactly what happens is an analogue problem, not a digital one, so it will depend on the exact model of CPU, the variations of chip manufacture, the power supply and the temperature. We can't even model this without knowing the transistor strengths and having some idea of the transistor parameters - which we can only guess at.

The RDY input is a more digital influence on the outcome. RDY is intended to stall the CPU during read accesses, so it can read from slow memory. As it happens, the 6502 samples the databus on every falling clock edge, and loads the IDL (Input Data Latch), and then drives into the target register. Normally, the final cycle is the one which counts, overwriting the stray external values. In some computers, RDY is used to stall the CPU while the bus is used for DMA, which means the bus contains data such as video data for several cycles, except the last. In the case of XAA, every cycle's data is ANDed into A, and this is why the final value of A changes even for the same values of operand, X and A.

Here's an abridged circuit diagram. Note that bits 0 and 4 have direct A feedback whereas the other bits have indirect feedback. Note that phi1 is when A is written, but the preceding phi2 is when the operand is loaded and the two busses precharged high.


(Logic gate pullups shown as resistors, although in NMOS logic pullups are not usually depletion-mode transistors. They pull up to the positive rail. The pass transistors and precharges cannot pull up to the rail: they drop a threshold voltage. These considerations will affect an analogue analysis.)

Tested CPUs

The base formula for XAA seens to be:

A = (A | magic) & X & imm

"magic" defines which bits of A shine through.

# Markings device tested in tester magic RDY clears #4 stable* notes
VC1541 Michael EE  ? yes this is the chip that came with this disk drive
VC1541 Michael EE  ? yes SALLY from my Atari 800
3 R6502P
VC1541 Michael FF  ? yes Simon's; spare part bought from retailer
C64, NTSC, old board Michael FF no yes
C64, NTSC, old board Michael FF no yes
C64, PAL, old (intermediate) board Michael FE yes yes
PAL C64, new board Michael FE yes yes
VC1571 Michael  ??  ? no very unstable; 1 MHz mode tested; can also do 2 MHz
9 SY
VC1541 Michael Simon's; yet to test
10 MOS
C128 Michael yet to test; can do 1 MHz and 2 MHz

(*)Note: "stable" means that the formula, the "magic" value and the potential #4 clearing by RDY fully describe the behavior.


  • For a list of all opcodes and some explanation of what they do, see 6502 all 256 Opcodes.
  • For notes on other opcodes we've explored in our simulations, see here.
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