6502 Timing of Interrupt Handling

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This page contains some as-yet unpolished extracts from postings by user Hydrophilic on commodore128.org, material used by permission.

This page contains work in progress and unanswered questions, which should be answered by reference to visual6502 simulation URLs.


Interrupt handling sequence

The 6502 performs an interrupt as a 7-cycle instruction sequence which starts with an instruction fetch. (Is this true when the interrupted instruction is a branch?) The fetched instruction is substituted by a BRK in the IR.

Interrupts colliding

  • this needs to be studied and verified. Observations by Hydrophilic follow

This simulation shows a lost NMI. NMI is brought low when doing an IRQ acknowledge. Specifically, 1/2 cycle before fetching the IRQ vector (cycle 13 phase 2). NMI remains low for 2.5 cycles. NMI returns high on cycle 16 phase 1.

The NMI is never serviced. This *might* be due #NMIP being automatically cleared after fetching PC high during any interrupt response...

Interrupts and changes to I mask bit

Instructions such as SEI and CLI affect the status register during the following instruction, due the the 6502 pipelining. Therefore the masking of the interrupt does not take place until the following instruction is already underway. However, RTI restores the status register early, and so the restored I mask bit already is in effect for the next instruction.

Interrupts during branches


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