6502 Unsupported Opcodes

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(KIL)
(add ANE aka XAA)
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* [http://visual6502.org/JSSim/expert.html?graphics=f&steps=16&a=5555&d=44&a=0&d=af5555ea&loglevel=2&logmore=dpc3_SBX,dpc23_SBAC,plaOutputs,DPControl LAX] will load both A and X - notice signals SBX and SBAC which control the writes to X and to A.
* [http://visual6502.org/JSSim/expert.html?graphics=f&steps=16&a=5555&d=44&a=0&d=af5555ea&loglevel=2&logmore=dpc3_SBX,dpc23_SBAC,plaOutputs,DPControl LAX] will load both A and X - notice signals SBX and SBAC which control the writes to X and to A.
* [http://visual6502.org/JSSim/expert.html?graphics=f&steps=26&a=0&d=ea42eaea&loglevel=2 KIL] will put the T-state counter into an unrecoverable state
* [http://visual6502.org/JSSim/expert.html?graphics=f&steps=26&a=0&d=ea42eaea&loglevel=2 KIL] will put the T-state counter into an unrecoverable state
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* [http://visual6502.org/JSSim/expert.html?graphics=f&steps=26&a=0&d=a9ffa2f08b5aeaea&loglevel=2&logmore=DPControl XAA #$5A] (also known as ANE) with A=FF
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  * and [http://visual6502.org/JSSim/expert.html?graphics=f&steps=26&a=0&d=a900a2f08b5aeaea&loglevel=2&logmore=DPControl with A=00] shows A is OR with 00 before AND with X and the immediate value
== some background ==
== some background ==

Revision as of 18:01, 5 January 2011

The 6502 is famous for doing interesting and sometimes useful things when the program includes invalid (or unspecified) opcodes.

The visual6502 simulator can help when investigating what these opcodes do, and why - see below!

examples

  • LAX will load both A and X - notice signals SBX and SBAC which control the writes to X and to A.
  • KIL will put the T-state counter into an unrecoverable state
  • XAA #$5A (also known as ANE) with A=FF
 * and with A=00 shows A is OR with 00 before AND with X and the immediate value

some background

Beware: different revisions of 6502 and versions from different manufacturers may have different behaviours.

For some of these opcodes, the chip does something logically predictable and our model has the same behaviour. But there may be opcodes which are not logically predictable, because they cause marginal voltages on the chip as different drivers fight one another, or a node which is undriven is sampled at a later time. In those cases, our visual6502 simulator, which is just a switch-level simulator with a couple of coarse heuristics for modelling contention and charge storage, won't do the same as a chip.

In fact, as some opcodes produce results which vary from one chip to another, no deterministic simulator could be 'accurate'. (A simulator could let you know that something is amiss)

But note that the underlying circuit data which we now have includes transistor strengths and an approximation of capacitative load: it could easily be extended for resistance and more accurate capacitance. So a more refined (lower level) simulation might shed more light on these undocumented opcodes. In fact, the FPGA model works differently - it moves charge from one node to another - and it might be more accurate for the difficult cases.

resources

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