6502 datapath

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This page discusses the 6502 datapath, using the terminology from [[Hanson's Block Diagram]] and is probably best understood by [http://www.pagetable.com/?p=39 reference to it]
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We're interested in which datapath control signals are active in each of the two phases.
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First the external bus.  DOR is latched from DB during phi1,
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All datapath control signals are latched at the end of phi2, i.e. the start of a full cycle. We describe their timing from that point onward, working broadly from left to right.
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and driven in phi2, if a write is done (and DBE is on, on the
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6501 -- DBE is an asynchronous signal).
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DL is latched during phi2, and then put on ADL, ADH, or DB on
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the next phi1 and phi2.
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ABL and ABH can be loaded from ADL and ADH resp. during phi1.
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=== External busses and signals ===
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R/#W is set during phi1 as well.
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DOR is latched from DB during phi1, and driven in phi2, if a write is done (and, on the 6501, when the asynchronous DBE is on).
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DL is latched during phi2, and then put on ADL, ADH, or DB on the next phi1 and phi2.
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All datapath control signals are latched at the end of phi2,
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ABL and ABH can be loaded from ADL and ADH respectively during phi1.
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i.e. the start of a full cycle.  I'll describe their timing
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from that point onward.
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R/#W is set during phi1 as well.
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ADL/ABL, ADH/ABH:
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=== Address values ===
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We already saw those.  Effective on phi1.
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0/ADL0, 0/ADL1, 0/ADL2, 0/ADH0, 0/ADH(1-7)
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; ADL/ABL, ADH/ABH:
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These set the interrupt vector fetch address, and the zero
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: We already saw these.  Effective on phi1.
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page and stack high address.  Effective on phi1 and phi2.
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; 0/ADL0, 0/ADL1, 0/ADL2, 0/ADH0, 0/ADH(1-7)
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: These set the interrupt vector fetch address, and the zero page and stack high address.  Effective on phi1 and phi2.
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Y/SB, X/SB, SB/Y, SB/X
 
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Move the X and Y registers from/to the SB.  Effective on phi1.
 
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=== The register file ===
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; Y/SB, X/SB, SB/Y, SB/X
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: Move the X and Y registers from/to the SB.  Effective on phi1.
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SB/S, S/S,  effective on phi1;
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; SB/S, S/S,  effective on phi1.
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S/SB, S/ADL,  effective on phi1 and phi2.
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; S/SB, S/ADL,  effective on phi1 and phi2.
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The S register is actually two latches in series.  This makes
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: The S register is actually two latches in series.  This makes it possible to read a value from SB and write a value to ADL at the same time.  On phi2, the value from the "in" latch is forwarded to the "out" latch (and onto the driven bus, if any).
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it possible to read a value from SB and write a value to ADL
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at the same time.  On phi2, the value from the "in" latch is
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forwarded to the "out" latch (and onto the driven bus, if any).
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(Note the [[6502 datapath control timing fix|two "tuning fork" structures]], which have contacts
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either on the top or bottom, which select whether X, Y, A write SB
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and DB only during phi1, or slightly longer, during "not phi2". We think this might be a timing fix, or an option left open until after silicon showed which choice worked best)
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[ By the way, the two "tuning fork" structures, which have contacts
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=== ALU inputs ===
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either on the top or bottom, select whether X, Y, A write SB
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; SB/ADD, 0/ADD, nDB/ADD, DB/ADD, ADL/ADD
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and DB only during phi1, or slightly longer, during "not phi2".
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: Two options for one side, three for the other.  Effective on phi1.
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I suppose they weren't sure which of the two would work best? ]
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=== ALU operation selection ===
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; ANDS, EORS, ORS, 1/ADDC, SRS, SUMS, DAA, DSA
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: Select the ALU operation. Effective on phi2 and the next phi1. During phi1 it will compute garbage.
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Now the ALU.  First the inputs:
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(The overflow and carry out signals AVR and ACR are output from the ALU back to the control logic,
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SB/ADD, 0/ADD, nDB/ADD, DB/ADD, ADL/ADD
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Two options for one side, three for the other.  Effective on phi1.
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ANDS, EORS, ORS, 1/ADDC, SRS, SUMS, DAA, DSA
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What operation to do.  Effective on phi2 and the next phi1.
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During phi1 it will compute garbage.
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(AVR and ACR are output from the ALU back to the control logic,
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latched at the end of phi2.  The decimal carries are latched
latched at the end of phi2.  The decimal carries are latched
then as well).
then as well).
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=== ALU output register ===
The ALU output register (ADD) is written during phi2.  The
The ALU output register (ADD) is written during phi2.  The
value can be used the next cycle:
value can be used the next cycle:
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ADD/SB7, ADD/SB(0-6), ADD/ADL, effective on phi1 and phi2.
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; ADD/SB7, ADD/SB(0-6), ADD/ADL, effective on phi1 and phi2.
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The ADL output is for address calculations.  For output to SB, the
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: The ADL output is for address calculations.  For output to SB, the top bit is handled separately for rotate right instructions: the ALU always computes a zero there; by not driving it to the bus a one will be read.
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top bit is handled separately for rotate right instructions: the
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ALU always computes a zero there, by not driving it to the bus a
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one can be made.
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SB/AC, effective on phi1.
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Lines 1-3,5-7 are fed through the decimal adjust first, to finish
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the proper BCD add/subtract result if necessary, before writing it
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to the accumulator.
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AC/SB, AC/DB, effective on phi1:
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write the A reg back to one of the busses.
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Almost done...
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; SB/AC, effective on phi1.
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: Lines 1-3,5-7 are fed through the decimal adjust first, to finish the proper BCD add/subtract result if necessary, before writing it to the accumulator.
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The PC:
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; AC/SB, AC/DB, effective on phi1
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: write the A reg back to one of the busses.
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ADH/PCH, PCH/PCH, PCL/PCL, ADL/PCL
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=== The Program Counter ===
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select whether to use the current PC, or take a new value
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from the internal address busses.  Effective on phi1.
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PCH/DB, PCL/DB, PCH/ADH, PCL/ADL
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; ADH/PCH, PCH/PCH, PCL/PCL, ADL/PCL
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write the PC to one of the busses.  Effective on phi1 and
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: select whether to use the current PC, or take a new value from the internal address busses.  Effective on phi1.
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phi2.  On phi1, it's the old value, on phi2, the new.
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I/PC, effective during phi2 and the next phi1:
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; PCH/DB, PCL/DB, PCH/ADH, PCL/ADL
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increment the PC, or not.
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: write the PC to one of the busses.  Effective on phi1 and phi2.  On phi1, it's the old value, on phi2, the new.
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; I/PC, effective during phi2 and the next phi1:
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: increment the PC, or not.
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Oh, I skipped P/DB.  It writes the flag values to the DB;
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;P/DB
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effective on phi1 and phi2.  The DB can be read to set
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: Write the flag values to the DB; effective on phi1 and phi2.  The DB can be read to set the flag values as well; it is read during phi1.
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the flag values as well; it is read during phi1.
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; SB/DB, SB/ADH
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: Connect two busses together.  Effective on phi1 and phi2.
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Finally:
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=== A note on signal naming ===
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In our [http://visual6502.org/JSSim/expert.html?graphics=f&logmore=DPControl&steps=10 Javascript simulation] the datapath control signals are tabulated according to Hanson's names, but [http://visual6502.org/JSSim/expert.html?nosim=t&find=dpc4_SSB,dpc5_SADL,dpc6_SBS,dpc7_SS&panx=166.0&pany=357.3&zoom=6.2 in the layout] they are named with a prefix according to their position across the chip. So
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* SSB, SADL, SBS, SS
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will be found as
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* dpc4_SSB,dpc5_SADL,dpc6_SBS,dpc7_SS
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SB/DB, SB/ADH
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=== Precharge ===
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Connect two busses together. Effective on phi1 and phi2.
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Several of the internal busses are driven high during phi2, as a sort of precharge. In fact commonly they are also driven by data signals during phi2, causing an intermediate voltage to appear on the bus.

Revision as of 10:51, 18 February 2011

This page discusses the 6502 datapath, using the terminology from Hanson's Block Diagram and is probably best understood by reference to it

We're interested in which datapath control signals are active in each of the two phases.

All datapath control signals are latched at the end of phi2, i.e. the start of a full cycle. We describe their timing from that point onward, working broadly from left to right.

Contents

External busses and signals

DOR is latched from DB during phi1, and driven in phi2, if a write is done (and, on the 6501, when the asynchronous DBE is on).

DL is latched during phi2, and then put on ADL, ADH, or DB on the next phi1 and phi2.

ABL and ABH can be loaded from ADL and ADH respectively during phi1.

R/#W is set during phi1 as well.

Address values

ADL/ABL, ADH/ABH
We already saw these. Effective on phi1.
0/ADL0, 0/ADL1, 0/ADL2, 0/ADH0, 0/ADH(1-7)
These set the interrupt vector fetch address, and the zero page and stack high address. Effective on phi1 and phi2.


The register file

Y/SB, X/SB, SB/Y, SB/X
Move the X and Y registers from/to the SB. Effective on phi1.
SB/S, S/S, effective on phi1.
S/SB, S/ADL, effective on phi1 and phi2.
The S register is actually two latches in series. This makes it possible to read a value from SB and write a value to ADL at the same time. On phi2, the value from the "in" latch is forwarded to the "out" latch (and onto the driven bus, if any).

(Note the two "tuning fork" structures, which have contacts either on the top or bottom, which select whether X, Y, A write SB and DB only during phi1, or slightly longer, during "not phi2". We think this might be a timing fix, or an option left open until after silicon showed which choice worked best)

ALU inputs

SB/ADD, 0/ADD, nDB/ADD, DB/ADD, ADL/ADD
Two options for one side, three for the other. Effective on phi1.

ALU operation selection

ANDS, EORS, ORS, 1/ADDC, SRS, SUMS, DAA, DSA
Select the ALU operation. Effective on phi2 and the next phi1. During phi1 it will compute garbage.

(The overflow and carry out signals AVR and ACR are output from the ALU back to the control logic, latched at the end of phi2. The decimal carries are latched then as well).

ALU output register

The ALU output register (ADD) is written during phi2. The value can be used the next cycle:

ADD/SB7, ADD/SB(0-6), ADD/ADL, effective on phi1 and phi2.
The ADL output is for address calculations. For output to SB, the top bit is handled separately for rotate right instructions: the ALU always computes a zero there; by not driving it to the bus a one will be read.
SB/AC, effective on phi1.
Lines 1-3,5-7 are fed through the decimal adjust first, to finish the proper BCD add/subtract result if necessary, before writing it to the accumulator.
AC/SB, AC/DB, effective on phi1
write the A reg back to one of the busses.

The Program Counter

ADH/PCH, PCH/PCH, PCL/PCL, ADL/PCL
select whether to use the current PC, or take a new value from the internal address busses. Effective on phi1.
PCH/DB, PCL/DB, PCH/ADH, PCL/ADL
write the PC to one of the busses. Effective on phi1 and phi2. On phi1, it's the old value, on phi2, the new.
I/PC, effective during phi2 and the next phi1
increment the PC, or not.
P/DB
Write the flag values to the DB; effective on phi1 and phi2. The DB can be read to set the flag values as well; it is read during phi1.
SB/DB, SB/ADH
Connect two busses together. Effective on phi1 and phi2.

A note on signal naming

In our Javascript simulation the datapath control signals are tabulated according to Hanson's names, but in the layout they are named with a prefix according to their position across the chip. So

  • SSB, SADL, SBS, SS

will be found as

  • dpc4_SSB,dpc5_SADL,dpc6_SBS,dpc7_SS

Precharge

Several of the internal busses are driven high during phi2, as a sort of precharge. In fact commonly they are also driven by data signals during phi2, causing an intermediate voltage to appear on the bus.

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