6502 datapath

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First the external bus. DOR is latched from DB during phi1, and driven in phi2, if a write is done (and DBE is on, on the 6501 -- DBE is an asynchronous signal). DL is latched during phi2, and then put on ADL, ADH, or DB on the next phi1 and phi2.

ABL and ABH can be loaded from ADL and ADH resp. during phi1. R/#W is set during phi1 as well.

All datapath control signals are latched at the end of phi2, i.e. the start of a full cycle. I'll describe their timing from that point onward.

ADL/ABL, ADH/ABH: We already saw those. Effective on phi1.

0/ADL0, 0/ADL1, 0/ADL2, 0/ADH0, 0/ADH(1-7) These set the interrupt vector fetch address, and the zero page and stack high address. Effective on phi1 and phi2.

Y/SB, X/SB, SB/Y, SB/X Move the X and Y registers from/to the SB. Effective on phi1.

SB/S, S/S, effective on phi1; S/SB, S/ADL, effective on phi1 and phi2. The S register is actually two latches in series. This makes it possible to read a value from SB and write a value to ADL at the same time. On phi2, the value from the "in" latch is forwarded to the "out" latch (and onto the driven bus, if any).

[ By the way, the two "tuning fork" structures, which have contacts either on the top or bottom, select whether X, Y, A write SB and DB only during phi1, or slightly longer, during "not phi2". I suppose they weren't sure which of the two would work best? ]

Now the ALU. First the inputs:

SB/ADD, 0/ADD, nDB/ADD, DB/ADD, ADL/ADD Two options for one side, three for the other. Effective on phi1.

ANDS, EORS, ORS, 1/ADDC, SRS, SUMS, DAA, DSA What operation to do. Effective on phi2 and the next phi1. During phi1 it will compute garbage.

(AVR and ACR are output from the ALU back to the control logic, latched at the end of phi2. The decimal carries are latched then as well). The ALU output register (ADD) is written during phi2. The value can be used the next cycle:

ADD/SB7, ADD/SB(0-6), ADD/ADL, effective on phi1 and phi2. The ADL output is for address calculations. For output to SB, the top bit is handled separately for rotate right instructions: the ALU always computes a zero there, by not driving it to the bus a one can be made.

SB/AC, effective on phi1. Lines 1-3,5-7 are fed through the decimal adjust first, to finish the proper BCD add/subtract result if necessary, before writing it to the accumulator.

AC/SB, AC/DB, effective on phi1: write the A reg back to one of the busses.

Almost done...

The PC:

ADH/PCH, PCH/PCH, PCL/PCL, ADL/PCL select whether to use the current PC, or take a new value from the internal address busses. Effective on phi1.

PCH/DB, PCL/DB, PCH/ADH, PCL/ADL write the PC to one of the busses. Effective on phi1 and phi2. On phi1, it's the old value, on phi2, the new.

I/PC, effective during phi2 and the next phi1: increment the PC, or not.

Oh, I skipped P/DB. It writes the flag values to the DB; effective on phi1 and phi2. The DB can be read to set the flag values as well; it is read during phi1.


SB/DB, SB/ADH Connect two busses together. Effective on phi1 and phi2.

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