6502 datapath control timing fix
A couple of transistors are connected to one clock, but the poly shows evidence that they used to be connected to another. [http://visual6502.org/JSSim/expert.html?nosim=t&find=cclk&panx=120.8&pany=307.6&zoom=12.4 See the missing contacts here].
That is, the gates were originally laid out so they could be clocked by not-phi1 but in fact are clocked by phi2. They control the X and the Y driving onto SB (special bus). There's another pair like them further along, which control the driving of the A onto the SB and the IDB. Seems like a fix for a timing marginality?