6502 increment PC control

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m (Protected "6502 increment PC control" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite)))
(added logic diagram and some commentary)
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Here's the layout, as rendered by [http://visual6502.org/JSSim/expert.html?nosim=t&find=short-circuit-branch-add,379&panx=381.0&pany=284.0&zoom=8.0 visual6502's JSSim]:
Here's the layout, as rendered by [http://visual6502.org/JSSim/expert.html?nosim=t&find=short-circuit-branch-add,379&panx=381.0&pany=284.0&zoom=8.0 visual6502's JSSim]:
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[[File:6502-ipc-layout.png]]
[[File:6502-ipc-layout.png]]
The highlighted signal bottom centre is the negative-sense signal "dpc36_#IPC", and the highlighted signal near the middle is "short-circuit-branch-add"
The highlighted signal bottom centre is the negative-sense signal "dpc36_#IPC", and the highlighted signal near the middle is "short-circuit-branch-add"
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Here's a diagram of the final few logic stages:
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[[File:6502-ipc-logic.png]]
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Note that the pulldown on the short-circuit-branch-add signal should be understood to override the output of the exclusive or.  The exclusive OR is implemented as a modified multiplexor - the modification ensures that the pulldown doesn't affect the signal notALUcout (node 206) which is used elsewhere, by pulling it down through the multiplexor's pass transitors.

Revision as of 14:06, 20 February 2011

The 6502 Program Counter has a dedicated incrementer which has to be able to increment across 16 bits in a single cycle.

It always increments during an instruction fetch cycle, to fetch a possible operand, but in general the decision whether or not to increment is a complex one.

As it happens, some of the logic implementing that decision is absent from Balazs' schematic, probably because of a bad patch in the die photograph. It also happens to use some unusual NMOS logic techniques.

Here's the layout, as rendered by visual6502's JSSim:

6502-ipc-layout.png

The highlighted signal bottom centre is the negative-sense signal "dpc36_#IPC", and the highlighted signal near the middle is "short-circuit-branch-add"

Here's a diagram of the final few logic stages:

6502-ipc-logic.png

Note that the pulldown on the short-circuit-branch-add signal should be understood to override the output of the exclusive or. The exclusive OR is implemented as a modified multiplexor - the modification ensures that the pulldown doesn't affect the signal notALUcout (node 206) which is used elsewhere, by pulling it down through the multiplexor's pass transitors.

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