650X Schematic Notes

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Notes on the original 650X schematics from MOS Technology, as safeguarded by Donald F Hanson.
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Notes on the original 650X schematics from MOS Technology.
=== Origin ===
=== Origin ===
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In 1979, Donald F Hanson sought original design data for microprocessors and contacted several microelectronics companies. MOS Technology provided him with blueprint copies of two sheets which make up the logic diagram for a 6502-series microprocessor.
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Donald F. Hanson, Ph.D., had written a 1995 paper based in part on the 6502 blueprints.  His original work was to reverse engineer a detailed [[Hanson%27s_Block_Diagram|block diagram]] of the processor. At the time he received the blueprints from MOS Technology in 1979, he had agreed to keep them confidential, except for educational use.  Earlier this year (2011), visual6502.org contacted Dr. Hanson.  After some negotiations, he agreed to provide scans of the original blueprints, for educational use only.  The blueprints he received were labeled Rev. C and contained a preliminary design.  Since the complete and error-free design (which we refer to as Rev D) is already known through the work of visual6502.org, Dr. Hanson felt that he could provide the Rev. C blueprints to visual6502.org for their historical value, provided that they be used for educational use.
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[[File:6502 rb sheet1-11-74.id.jpeg|400px|thumb|right|ID from sheet 1]]  
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[[File:6502 schematic sheet1-11-74.id.jpeg|400px|thumb|right|ID from sheet 1]]  
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[[File:6502 dc sheet2-8-12-75.id.jpeg|400px|thumb|right|ID from sheet 2]]  
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[[File:6502 schematic sheet2-8-12-75.id.jpeg|400px|thumb|right|ID from sheet 2]]  
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In 2011 he kindly forwarded scans of these two sheets to the visual6502 project and agreed that we could show details from them with a credit line as follows:
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=== Overview ===
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  Credit:  “MOS Technology, 1974-75, 6502 rev C, for educational use only.”
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For further details of his improved modelling language for MOS design, see [[http://www.witwright.com/DonPub/DSH_6502_ComputerArch.pdf his paper]].
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Description and images of the two sheets, which will contain side text 'Courtesy...'
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We thank Dr Hanson for these materials.  Our analysis of the schematics follows below.
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Mention the dates on the ID labels, the very close correspondence to chip layout.
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=== Overview ===
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=== Pin Names ===
=== Pin Names ===
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Mention at least SYNC and SO pin names, also the names on unbonded pins.
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Image of SO/C.P.S pin, and link to an account of 'Chuck Peddle Special'
=== Chip Versions: 6501 and 6502 ===
=== Chip Versions: 6501 and 6502 ===
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Describe and illustrate the X/O boxes (around top edge of diagram)
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Mention the 6501/6502 differences including the SYNC pin.
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Also mention the 6504 (?)
=== Chip Revision C, ROR Bug, Other Errors ===
=== Chip Revision C, ROR Bug, Other Errors ===
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Mention and illustrate the missing/extra transistors in the PLA which give rise to the ROR bug
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Also mention the other discrepancies in the PLA
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Any other Rev C versus Rev D observations
=== Schematic Errors ===
=== Schematic Errors ===
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TBD
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=== Logic gates and Transistors ===
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Mention and illustrate the presence of gates and transistors, the transistor sizes and die sizes in mils (thousandths of inch) and the presence of internal signal names - use the cross-coupled D1x1 latch to illustrate.  Compare with Balazs' schematic.
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=== Acknowledgements ===
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Thanks to the following for their observations and assistance
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* Edgar F
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* Segher Boessenkool
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* Michael Steil
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* Donald F Hanson, for making the scans of the 6502 available to us, and
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** Department of Electrical Engineering, University of Mississippi, University, MS, for supporting Prof. Hanson’s work on the 6502 including the drafting of the [[Hanson%27s_Block_Diagram|block diagram]].
=== References ===
=== References ===
* Donald F. Hanson, [[http://www.witwright.com/DonPub/DSH_6502_ComputerArch.pdf "A VHDL Conversion Tool for Logic Equations with Embedded D Latches,"]], Technical Committee on Computer Architecture Newsletter, pp. 49-56, Spring 1995, IEEE Computer Society.
* Donald F. Hanson, [[http://www.witwright.com/DonPub/DSH_6502_ComputerArch.pdf "A VHDL Conversion Tool for Logic Equations with Embedded D Latches,"]], Technical Committee on Computer Architecture Newsletter, pp. 49-56, Spring 1995, IEEE Computer Society.

Revision as of 16:02, 28 October 2011

Notes on the original 650X schematics from MOS Technology.

Contents

Origin

Donald F. Hanson, Ph.D., had written a 1995 paper based in part on the 6502 blueprints. His original work was to reverse engineer a detailed block diagram of the processor. At the time he received the blueprints from MOS Technology in 1979, he had agreed to keep them confidential, except for educational use. Earlier this year (2011), visual6502.org contacted Dr. Hanson. After some negotiations, he agreed to provide scans of the original blueprints, for educational use only. The blueprints he received were labeled Rev. C and contained a preliminary design. Since the complete and error-free design (which we refer to as Rev D) is already known through the work of visual6502.org, Dr. Hanson felt that he could provide the Rev. C blueprints to visual6502.org for their historical value, provided that they be used for educational use.

ID from sheet 1
ID from sheet 2

Overview

Description and images of the two sheets, which will contain side text 'Courtesy...'

Mention the dates on the ID labels, the very close correspondence to chip layout.

Pin Names

Mention at least SYNC and SO pin names, also the names on unbonded pins.

Image of SO/C.P.S pin, and link to an account of 'Chuck Peddle Special'

Chip Versions: 6501 and 6502

Describe and illustrate the X/O boxes (around top edge of diagram)

Mention the 6501/6502 differences including the SYNC pin.

Also mention the 6504 (?)

Chip Revision C, ROR Bug, Other Errors

Mention and illustrate the missing/extra transistors in the PLA which give rise to the ROR bug

Also mention the other discrepancies in the PLA

Any other Rev C versus Rev D observations

Schematic Errors

TBD

Logic gates and Transistors

Mention and illustrate the presence of gates and transistors, the transistor sizes and die sizes in mils (thousandths of inch) and the presence of internal signal names - use the cross-coupled D1x1 latch to illustrate. Compare with Balazs' schematic.

Acknowledgements

Thanks to the following for their observations and assistance

  • Edgar F
  • Segher Boessenkool
  • Michael Steil
  • Donald F Hanson, for making the scans of the 6502 available to us, and
    • Department of Electrical Engineering, University of Mississippi, University, MS, for supporting Prof. Hanson’s work on the 6502 including the drafting of the block diagram.

References

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