650X Schematic Notes
Notes on the original 650X schematics from MOS Technology.
In 1995 Donald F. Hanson, Ph.D., published a paper based in part on the 6502 blueprints. His original work was to reverse engineer a detailed block diagram of the processor. At the time he received the blueprints from MOS Technology in 1979, he had agreed to keep them confidential, except for educational use. Earlier this year (2011), visual6502.org contacted Dr. Hanson. After some negotiations, he agreed to provide scans of the original blueprints, for educational use only. The blueprints he received were labeled Rev. C and contained a preliminary design. Since the complete and error-free design (which we refer to as Rev D) is already known through the work of visual6502.org, Dr. Hanson felt that he could provide the Rev. C blueprints to visual6502.org for their historical value, provided that they be used for educational use.
On this page we present some reduced-size images of those scans, and some findings from the information on them.
The two blueprints, or schematics, are approximately 1100mm by 1600mm (according to pdf metadata) and scanned at 400 dpi. The one labelled as 'Sheet 1' and 'bottom half' contains the register file, its drivers, and most of the data and address pads. It is dated '11/74' and bears the names Orgill and Mensch. The one labelled as 'Sheet 2' contains everything else (decode ROM, IR, control logic, timing logic, all the other pads) and is dated 8-12-75, again with the names of Orgill and Mensch.
The labels contain the description '650X-C Logic Diagram'
Both the broad organisation and the detailed location of every feature resembles that of the 6502 Rev D chip. These are therefore blueprints as much as they are schematics. The dates place them after the debut of the 6501 and 6502.
Some of the pad names are different from the modern 6502 pin names:
- pin 5 is labelled VMA (for 6800 compatibility), but is No Connect on 6502
- pin 7 is labelled T1, but is now known as Sync.
- pin 36 is labelled DBE (for 6800 compatibility), but is now No Connect
- pin 38 is labelled C.P.S. but is now known as SO for Set Overflow. There's a story about the naming of this pin.
Chip Versions: 6501 and 6502
Describe and illustrate the X/O boxes (around top edge of diagram)
Mention the 6501/6502 differences including the SYNC pin.
Also mention the 6504 (?)
Chip Revision C, ROR Bug, Other Errors
Mention and illustrate the missing/extra transistors in the PLA which give rise to the ROR bug
Also mention the other discrepancies in the PLA
Any other Rev C versus Rev D observations
Logic gates and Transistors
Mention and illustrate the presence of gates and transistors, the transistor sizes and die sizes in mils (thousandths of inch) and the presence of internal signal names - use the cross-coupled D1x1 latch to illustrate. Compare with Balazs' schematic.
Thanks to the following for their observations and assistance
- Edgar F
- Segher Boessenkool
- Michael Steil
- Donald F Hanson, for making the scans of the 6502 available to us
- Department of Electrical Engineering, University of Mississippi, University, MS, for supporting Prof. Hanson’s work on the 6502 including the drafting of the block diagram.
- Donald F. Hanson, ["A VHDL Conversion Tool for Logic Equations with Embedded D Latches,"], Technical Committee on Computer Architecture Newsletter, pp. 49-56, Spring 1995, IEEE Computer Society.