650X Schematic Notes

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Notes on the original 650X schematics from MOS Technology.



In 1995 Donald F. Hanson, Ph.D., published a paper based in part on the 6502 blueprints. His original work was to reverse engineer a detailed block diagram of the processor. At the time he received the blueprints from MOS Technology in 1979, he had agreed to keep them confidential, except for educational use. Earlier this year (2011), visual6502.org contacted Dr. Hanson. After some negotiations, he agreed to provide scans of the original blueprints, for educational use only. The blueprints he received were labeled Rev. C and contained a preliminary design. Since the complete and error-free design (which we refer to as Rev D) is already known through the work of visual6502.org, Dr. Hanson felt that he could provide the Rev. C blueprints to visual6502.org for their historical value, provided that they be used for educational use.

On this page we present some reduced-size images of those scans, and some findings from the information on them.

Sheet 2 Decode and Control (bears the date 8-12-75)
Sheet 1 "bottom half" Registers and Busses (bears the date 11/74)


The two blueprints, or schematics, are approximately 1100mm by 1600mm (according to pdf metadata) and scanned at 400 dpi. The one labelled as 'Sheet 1' and 'bottom half' contains the register file, its drivers, and most of the data and address pads. It is dated '11/74' and bears the names Orgill and Mensch. The one labelled as 'Sheet 2' contains everything else (decode ROM, IR, control logic, timing logic, all the other pads) and is dated 8-12-75, again with the names of Orgill and Mensch.

The labels contain the description '650X-C Logic Diagram'

Both the broad organisation and the detailed location of every feature resembles that of the 6502 Rev D chip. These are therefore blueprints as much as they are schematics. The dates place them after the debut of the 6501 and 6502.

ID from sheet 1 "bottom half" (bears the date 11/74)
ID from sheet 2 (bears the date 8-12-75)

Pin Names

Some of the pad names are different from the modern 6502 pin names:

  • pin 5 is labelled VMA (for 6800 compatibility), but is No Connect on 6502
  • pin 7 is labelled T1, but is now known as Sync.
  • pin 36 is labelled DBE (for 6800 compatibility), but is now No Connect
  • pin 38 is labelled C.P.S. but is now known as SO for Set Overflow. There's a story about the naming of this pin.


Chip Versions: 6501 and 6502

As mentioned, the labels indicate that these schematics cover 650X - more than one variant product. Along the top edge of the upper sheet there are several boxes marked with X or O which we believe allow for a 6501 or 6502 variant by changing only the metal mask, and only in a few places.

For example here are some options relating to the on-chip clocks, which differ depending on the use of the clock pins:


The T1 or SYNC pin is believed to require a slight change too between 6501 and 6502, which is possible in metal, but does not appear on the schematics.

The 6504 is a 28-pin version which requires the inputs NMI, RDY and SO to be tied-off. There is no hint of this in the schematic although a metal-only change is probably possible.

Chip Revision C, ROR Bug, Other Errors

Mention and illustrate the missing/extra transistors in the PLA which give rise to the ROR bug

Also mention the other discrepancies in the PLA

Any other Rev C versus Rev D observations

Schematic Errors


Logic gates and Transistors

Mention and illustrate the presence of gates and transistors, the transistor sizes and die sizes in mils (thousandths of inch) and the presence of internal signal names - use the cross-coupled D1x1 latch to illustrate. Compare with Balazs' schematic.


Thanks to the following for their observations and assistance

  • Edgar F
  • Segher Boessenkool
  • Michael Steil
  • Donald F Hanson, for making the scans of the 6502 available to us
  • Department of Electrical Engineering, University of Mississippi, University, MS, for supporting Prof. Hanson’s work on the 6502 including the drafting of the block diagram.


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