Revision as of 21:28, 17 May 2011 by EdS
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6502 netlist simulated in FPGA module in apple ][e clone at approx 1MHz (credit: Ingo Korb)
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|current||21:25, 17 May 2011||1,500×1,000 (191 KB)||EdS||(6502 netlist simulated in FPGA module in vintage 8-bit computer at approx 1MHz (credit: Ingo Korb))|