MOS 6502

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== MOS 6502 family ==
== MOS 6502 family ==
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We have photographs of the metal and lower layers, the polygons captured, the circuit extracted and we have published [http://visual6502.org/JSSim a javascript simulator].  There is an [https://github.com/pmonta/FPGA-netlist-tools FPGA project] to implement the simulation in hardware. We have (as yet) unpublished simulators in python and C.
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We have [[Photos of MOS 6502D|photographs of the metal and lower layers]], the polygons captured, the circuit extracted and we have published [http://visual6502.org/JSSim a javascript simulator].  There is an [https://github.com/pmonta/FPGA-netlist-tools FPGA project] to implement the simulation in hardware. We have (as yet) unpublished simulators in python and C.
== Our Analysis ==
== Our Analysis ==
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Here are some relatively raw materials we've collected:
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* Comparative photos of the [[6502 Stack Register High Bits|Stack Register]] in 6502 and 6507
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* The [[6507 Decode ROM|Decode ROM]] (describing the Atari 6507, not exactly the same as the NMOS 6502 used in the [http://visual6502.org/JSSim visual6502 simulator]
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* [[6502 all 256 Opcodes|All 256 6502 opcodes]] named and tabulated
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And here is some more interpretive material from our explorations:
* Collected [[6502Observations|observations]] of 6502 layout and behaviour.
* Collected [[6502Observations|observations]] of 6502 layout and behaviour.
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* [[6507 Decode ROM|Decode ROM]] (describing the Atari 6507, not exactly the same as the NMOS 6502 used in the [http://visual6502.org/JSSim visual6502 simulator]
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* The 6502 [[6502 datapath|datapath timing]]
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* [[6502 all 256 Opcodes|all 256 6502 opcodes]] including illegals and their actions
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* The [[6502_Unsupported_Opcodes|unsupported opcodes]]
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* [[6502 Stack Register High Bits|Stack Register]]
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** a detailed explanation of the [[6502 Opcode 8B (XAA, ANE)|XAA opcode]] behaviour
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* [[6502_-_simulating_in_real_time_on_an_FPGA|Implementing a realtime netlist simulation]] in historical systems using an FPGA
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= 6502 additional information =
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== 6502 additional information ==
See also the [http://visual6502.org/links.html links] page on the main site.
See also the [http://visual6502.org/links.html links] page on the main site.
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== Primary Sources ==
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=== Primary Sources ===
* [[Photos of MOS 6502D]] (also see our [http://visual6502.org/images/6502/index.html website])
* [[Photos of MOS 6502D]] (also see our [http://visual6502.org/images/6502/index.html website])
* [[Atari's 6507 Schematics]]
* [[Atari's 6507 Schematics]]
* [[Photos of R6502]]
* [[Photos of R6502]]
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== Secondary Sources ==
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=== Secondary Sources ===
* [[Hanson's Block Diagram]]
* [[Hanson's Block Diagram]]
* [[Balazs' schematic and documents]]
* [[Balazs' schematic and documents]]
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== Previous Analysis ==
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=== Previous Analysis ===
* [http://impulzus.sch.bme.hu/6502/letolt.php3 Beregnyei Balazs: 6502 Reverse Engineering] ([http://www.downloads.reactivemicro.com/Public/Electronics/Reverse%20Engineering/ translation])
* [http://impulzus.sch.bme.hu/6502/letolt.php3 Beregnyei Balazs: 6502 Reverse Engineering] ([http://www.downloads.reactivemicro.com/Public/Electronics/Reverse%20Engineering/ translation])
* [http://anyplatform.net/media/guides/cpus/65xx%20Processor%20Data.txt Mark Ormston: 65xx Processor Data (version 0.2b)]
* [http://anyplatform.net/media/guides/cpus/65xx%20Processor%20Data.txt Mark Ormston: 65xx Processor Data (version 0.2b)]

Latest revision as of 20:10, 12 May 2011

Contents

MOS 6502 family

We have photographs of the metal and lower layers, the polygons captured, the circuit extracted and we have published a javascript simulator. There is an FPGA project to implement the simulation in hardware. We have (as yet) unpublished simulators in python and C.

Our Analysis

Here are some relatively raw materials we've collected:

And here is some more interpretive material from our explorations:

6502 additional information

See also the links page on the main site.

Primary Sources

Secondary Sources

Previous Analysis

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