See here for an overview of the chip and the photographs we have of the die. As of late March 2011 we have vectorised polygons and a transistor level netlist, which we hope to publish soon.
Here are JPEG images of the recaptured polygons - these may be easier to explore than the svg format:
Interesting features (more detail to be added)
- register circuit
- data latch circuit
- clock pulse shaping
- bus pullup
- carry chain