NMOS Depletion Mode Transistors

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m (Protected "NMOS Depletion Mode Transistors" ([edit=autoconfirmed] (indefinite) [move=autoconfirmed] (indefinite)))
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The usual circuit design of a logic gate in NMOS technology is a network of pull-down transistors and a single pull-up. The pull-up will be a depletion mode device, and the gate will be connected to the logic gate's output. The depletion implant adjusts the transistor threshold to below zero volts, with the effect that such a pull-up transistor is always on, and the effect that the pull-up can pull all the way to the positive rail.  These pull-ups account for the higher power consumption of NMOS compared to the later CMOS technology.
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The usual circuit design of a logic gate in NMOS technology is a network of pull-down transistors and a single pull-up. The pull-up will be a depletion mode device, and the gate will be connected to the logic gate's output. The depletion implant adjusts the transistor threshold to below zero volts, with the effect that such a pull-up transistor is always on, and the effect that the pull-up can pull all the way to the positive rail; and it will conduct better at a lower voltage.  These pull-ups account for the higher power consumption of NMOS compared to the later CMOS technology.
Our problem in reverse-engineering NMOS chips is that the implant cannot be seen in our photographs.  (There may be staining techniques which will help but we haven't yet tried them.)
Our problem in reverse-engineering NMOS chips is that the implant cannot be seen in our photographs.  (There may be staining techniques which will help but we haven't yet tried them.)
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First, the easy cases:
First, the easy cases:
* all pull-downs are enhancement mode
* all pull-downs are enhancement mode
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* all pass gates are enhancement mode
* all transistors with gate connected to source are depletion mode
* all transistors with gate connected to source are depletion mode
Next, there are two cases we can be fairly sure of
Next, there are two cases we can be fairly sure of
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* clock drivers must have depletion mode pullups because they need logic 1 to reach the rail
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* clock drivers must have depletion mode pullups because they need logic 1 to reach the rail  
* the huge pull-ups at the output pads will be enhancement mode, which means a logic 0 will pull down to ground, and a logic 1 will be a volt or so less than the positive rail.
* the huge pull-ups at the output pads will be enhancement mode, which means a logic 0 will pull down to ground, and a logic 1 will be a volt or so less than the positive rail.
* a conventional super buffer circuit with a single pullup driven by the inverse of the single pulldown will have a depletion mode pullup
* a conventional super buffer circuit with a single pullup driven by the inverse of the single pulldown will have a depletion mode pullup
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Here are some cases found on the 6502 which require some judgement and explanation:
Here are some cases found on the 6502 which require some judgement and explanation:
* t481, t1169, t1344, t1035 (all in the clock generation)
* t481, t1169, t1344, t1035 (all in the clock generation)
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* t2544, t11  (local clock drivers?)
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* t2544, t11  (inverse of phi1, used to pull down some of the datapath control signals)
* t1477 (timing generator)
* t1477 (timing generator)
* Datapath control line drivers (t1527, t439, ..., t2326)
* Datapath control line drivers (t1527, t439, ..., t2326)
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* t2523, t76, t2179, t362 in the clock again, but second stage drivers this time.  Huge huge pulldowns.
* t2523, t76, t2179, t362 in the clock again, but second stage drivers this time.  Huge huge pulldowns.
* t1322, the dead PLA line.
* t1322, the dead PLA line.
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(All of these are depletion on the Rockwell and Atari 6507+6532 schematics; could not verify SYNC and R/#W and the external clock outputs on those).
(Need to convert the above into links: [http://visual6502.org/JSSim/expert.html?nosim=t&find=t3353 t3353] ADL bus precharge
(Need to convert the above into links: [http://visual6502.org/JSSim/expert.html?nosim=t&find=t3353 t3353] ADL bus precharge
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The precharges for all four internal busses are enhancement mode.

Revision as of 13:07, 5 February 2011

The usual circuit design of a logic gate in NMOS technology is a network of pull-down transistors and a single pull-up. The pull-up will be a depletion mode device, and the gate will be connected to the logic gate's output. The depletion implant adjusts the transistor threshold to below zero volts, with the effect that such a pull-up transistor is always on, and the effect that the pull-up can pull all the way to the positive rail; and it will conduct better at a lower voltage. These pull-ups account for the higher power consumption of NMOS compared to the later CMOS technology.

Our problem in reverse-engineering NMOS chips is that the implant cannot be seen in our photographs. (There may be staining techniques which will help but we haven't yet tried them.)

So, having identified all the transistors on a chip such as the 6502, we have to engage in some deduction and guesswork to infer which transistors are depletion mode.

First, the easy cases:

  • all pull-downs are enhancement mode
  • all pass gates are enhancement mode
  • all transistors with gate connected to source are depletion mode

Next, there are two cases we can be fairly sure of

  • clock drivers must have depletion mode pullups because they need logic 1 to reach the rail
  • the huge pull-ups at the output pads will be enhancement mode, which means a logic 0 will pull down to ground, and a logic 1 will be a volt or so less than the positive rail.
  • a conventional super buffer circuit with a single pullup driven by the inverse of the single pulldown will have a depletion mode pullup

Here are some cases found on the 6502 which require some judgement and explanation:

  • t481, t1169, t1344, t1035 (all in the clock generation)
  • t2544, t11 (inverse of phi1, used to pull down some of the datapath control signals)
  • t1477 (timing generator)
  • Datapath control line drivers (t1527, t439, ..., t2326)
  • t2066 the tristate driver
  • t367, the driver for RDY.
  • t397 SYNC, t2208/t441 R/#W, t578/t3122 D1, and probably all the other first stage pin drivers.
  • t2523, t76, t2179, t362 in the clock again, but second stage drivers this time. Huge huge pulldowns.
  • t1322, the dead PLA line.

(All of these are depletion on the Rockwell and Atari 6507+6532 schematics; could not verify SYNC and R/#W and the external clock outputs on those).

(Need to convert the above into links: t3353 ADL bus precharge

The precharges for all four internal busses are enhancement mode.

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