Photos of MOS 6502D

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In the summer of 2009, the Visual6502.org project shot and assembled high resolution photographs of a MOS 6502 revD.  The surface of the chip was photographed, then the metal and polysilicon layers were stripped off to reveal the conductive substrate diffusion areas.  This substrate was photographed, and the substrate image was aligned to the surface image.  These two aligned images were used to create the vector polygons that from the Visual6502 chip simulation.
In the summer of 2009, the Visual6502.org project shot and assembled high resolution photographs of a MOS 6502 revD.  The surface of the chip was photographed, then the metal and polysilicon layers were stripped off to reveal the conductive substrate diffusion areas.  This substrate was photographed, and the substrate image was aligned to the surface image.  These two aligned images were used to create the vector polygons that from the Visual6502 chip simulation.
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[[File:6502_top_algn_01_quarterSize.png|200px|thumb|left]]
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[http://www.visual6502.org/images/6502/6502_top_algn_01_quarterSize.png]
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[http://www.visual6502.org/images/6502/6502_sub_algn_01_quarterSize.png]

Revision as of 08:43, 27 September 2010

In the summer of 2009, the Visual6502.org project shot and assembled high resolution photographs of a MOS 6502 revD. The surface of the chip was photographed, then the metal and polysilicon layers were stripped off to reveal the conductive substrate diffusion areas. This substrate was photographed, and the substrate image was aligned to the surface image. These two aligned images were used to create the vector polygons that from the Visual6502 chip simulation.

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