RCA 1802E

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The RCA 1802 was a pioneering CMOS microprocessor.

See our main site for some more information and images.

Not only was the C2L CMOS process simpler, denser and faster than previous ones, it lends itself to radiation-hard chips, which led to this CPU being found in various space probes. (The bulk silicon process used for our RCA 1802 is not as radiation tolerant as the later silicon-on-sapphire processes, but it was better than other contemporary processes.)

As it happens, it's also a great process for us to photograph and analyse, because the N and P structures show as different colours, and the layout is very readable. For the same reason, with this chip reverse-engineering the die photo may be feasible without needing to strip the metal.


Control Logic


This schematic was derived by tracing the excellent die photo, so the arrangement of the gates pretty much follows the layout on die. There are an extensive use of transparent latches of various enable and output polarities, which are denoted with squares.

The design is much more asynchronous than the 6502 or any of the later CPUs; the clock input at the far left goes through the wait/pause/reset logic, and basically only 2 blocks get clocked at the input rate, which is the signal coming out of U77: the sequencer, and the ALU.

The sequencer is a Johnson counter that uses latches, generating 8 phase-shifted signals I've named seq0 through seq7. It's located southeast of /tpa. Interestingly there's a patent (6020770) by Motorola several decades later on using transparent latches in a Johnson counter. Anyway, seq0-7 feed the logic to the right, which produces signals active for various periods of the sequence - I've denoted these CL0-F. As it's a latch-based design both rising and falling edges of the clock are used.

The ALU in the bottom left is serial and multiplexer-based. 3 latches above it pick off the lower 3 bits of the internal data bus to select the function. U123 is the main output (goes to D_SHIFT_IN of the datapath), and U63 is the carry out which goes to the carry flag latch U177.

North of the ALU, above the internal databus and below the clock/reset logic, is instruction decoding, fed from the 2-to-16 decoder to its left. Each line of 16 opcodes is decoded separately.

On the east, below the seq0-7 logic, is the main state machine with 4 latches for EXECUTE, INTERRUPT, FETCH, and DMA. Below that are latches for Q and the interrupt enable, as well as more datapath control logic. Finally, the top left corner contains the interrupt/DMA input circuitry.

[text contributed by AmyK]

Simple logic gates


Above we see a detail of our high-resolution images, showing several logic gates laid out with their complementary pullup and pulldown trees in their respective areas (Orange on green is NMOS, purple on blue is PMOS.) The power supply to each gate is the substrate (or well) so there are fewer contacts than in the usual technologies.

Middle-right is the simplest gate: an inverter, with a single pull-down and single pull-up. Above it is a 2-input NOR gate and to the left is a 3-input NOR gate. The three concentric transistors of the NOR3 are rarely seen on this chip, perhaps because of the reduced drive and speed of having 3 transistors in series.

NOR4 layout

If a NOR4 were laid out like the NOR3 above, it would be rather large because of the need for 4 concentric transistors. The largest (outside) transistors would present more load to their drivers, but wouldn't contribute more drive to the NOR4 because that will be limited by the innermost transistor.

So here we see an alternative layout technique, where an isolated region is created in the lower right, containing two of the pullups, the upper one of which is operated inside-out.



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