File list

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This special page shows all uploaded files. By default the last uploaded files are shown at top of the list.

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File list
 

descDate Name User Size Description Versions
08:55, 4 March 20131802_dpth-small.png (file)EdS173 KB (1802 datapath thumbnail)1
05:49, 4 March 20131802_dpth.png (file)AmyK180 KB (1802 datapath.)1
12:38, 4 February 2013Rca1802-control-reversed-small.gif (file)EdS46 KB (Resized version of File:Rca1802-control-reversed.gif (because auto-thumbnails are not working))1
12:19, 4 February 2013Rca1802-control-reversed.gif (file)EdS213 KB (Partial (reversed) schematic of the 1802 control logic, by AmyK)1
17:37, 9 September 20126502-decimal-DAA-removed-visual6502.png (file)EdS21 KB (Improved framing and reduced fuzz (using canvas=4000) )2
11:34, 9 September 2012NES-2A03-decimal-DAA-removed.png (file)EdS37 KB (Transistor t2556 is missing (shorted) - one of five so treated to remove decimal mode from the NES 2A03)1
11:26, 9 September 20126502-decimal-subtract-visual6502.png (file)EdS117 KB (Screenshot from visual6502 showing transistors t3212 and t1329, which were removed (shorted) in the NES 2A03 chip.)1
15:37, 9 April 2012650X-revC-ROR-pla.png (file)EdS60 KB (detail from 650X Schematic showing erroneous lines in the decoder responsible for the ROR bug)1
14:55, 9 April 2012650X-onchipclocking.png (file)EdS343 KB (detail from 650X Schematic showing some of the X/O boxes believed to indicate the 6501/6502 variations in metallisation.)1
14:47, 9 April 2012650X-CPS-pad.png (file)EdS122 KB (detail from 650X Schematic showing CPS pad 38 (modern SO, set overflow))1
09:42, 29 December 20116502_photo_wrong-clock-annot.jpg (file)EdS44 KB (Close up of R6502 layout showing datapath control lines clocked oddly with missing vias. Annotated to show present and missing contact cuts. )1
11:46, 7 November 20116502_schematic_sheet2-8-12-75.jpeg (file)EdS375 KB (Credit: MOS Technology Sheet 2 "650X-C Logic Diagram Microprocessor" "Engineering Approval by ORGILL, MENSCH" dated 8-12-75 Scan: Courtesy of Donald F. Hanson, Dept. of Elec. Engr., Univ. of Mississippi, University, MS 38677)1
11:45, 7 November 20116502_schematic_sheet1-11-74.jpeg (file)EdS97 KB (Credit: MOS Technology Sheet 1 "650X-C Microprocessor Logic Diagram (Bottom Half)" "Engineering Approval by ORGILL and MENSCH" dated 11/74 Scan: Courtesy of Donald F. Hanson, Dept. of Elec. Engr., Univ. of Mississippi, University, MS 38677)1
15:43, 28 October 20116502_schematic_sheet1-11-74.id.jpeg (file)EdS376 KB (Credit: MOS Technology Identification area from MOS Technology "650X-C Microprocessor Logic Diagram (Bottom Half)" sheet 1 "Engineering Approval by ORGILL and MENSCH" dated 11/74 Scan: Courtesy of Donald F. Hanson, Dept. of Elec. Engr., Univ. of Missis)1
15:39, 28 October 20116502_schematic_sheet2-8-12-75.id.jpeg (file)EdS388 KB (Credit: MOS Technology Identification area from MOS Technology "650X-C Logic Diagram Microprocessor" sheet 2 "Engineering Approval by ORGILL, MENSCH" dated 8-12-75 Scan: Courtesy of Donald F. Hanson, Dept. of Elec. Engr., Univ. of Mississippi, Universi)1
21:25, 17 May 20116502-fpga-apple2-overview-IMG_1086.jpg (file)EdS191 KB (6502 netlist simulated in FPGA module in vintage 8-bit computer at approx 1MHz (credit: Ingo Korb))1
21:24, 17 May 20116502-fpga-vic20-overview-IMG_1081.jpg (file)EdS234 KB (6502 netlist simulated in FPGA module in vintage 8-bit computer at approx 1MHz (credit: Ingo Korb))1
21:23, 17 May 20116502-fpga-c64-overview-IMG_1080.jpg (file)EdS271 KB (6502 netlist simulated in FPGA module in vintage 8-bit computer at approx 1MHz (credit: Ingo Korb))1
19:51, 12 May 20116502-fpga-apple2-img_0040.jpg (file)EdS2.69 MB (6502 netlist simulated in FPGA module in apple ][e clone)1
19:48, 12 May 20116502-fpga-vic20-img_0039.jpg (file)EdS2.22 MB (6502 netlist simulated in FPGA module in VIC20)1
18:22, 12 May 20116507-demo1.jpg (file)EdS279 KB (6502 netlist resimulated in FPGA acting as a 6507 in Atari system)1
18:19, 12 May 20116507-demo0.jpg (file)EdS231 KB (6502 netlist resimulated in FPGA acting as a 6507 in Atari system)1
17:51, 5 April 2011Mc6800a-Layout-svg-150h.jpg (file)EdS7 KB (Thumbnail of mc6800 layout (SVG format: polygons manually re-captured from microphotography))1
10:32, 28 March 2011M6800-arch.png (file)EdS183 KB (Motorola 6800 block diagram (Fig 2 from US Patent 3987418, 1976, fair use.))1
09:29, 13 March 2011Rca1802-detail2-nor4.png (file)EdS268 KB (change block-out colour to white)2
09:11, 13 March 2011Rca1802-detail-nor4.png (file)EdS473 KB (detail of a NOR4 (in non-concentric style) on the RCA1802E)1
17:24, 12 March 2011Rca1802-detail-annotated.jpg (file)EdS43 KB (Annotated detail showing a few CMOS logic gates on the RCA 1802)1
17:23, 12 March 2011Rca1802-detail.jpg (file)EdS40 KB (Detail showing a few CMOS logic gates on the RCA 1802)1
10:28, 21 February 20116502-ipc-circuit.png (file)EdS19 KB (bug fixes)2
18:10, 20 February 20116502-ipc-logic.png (file)EdS20 KB (rename a misnamed signal)4
16:44, 19 February 20116502-ipc-layout.png (file)EdS124 KB (Layout image from JSSim of the final logic stages leading to the 6502's incrementer enable input.)1
19:47, 10 January 20116502-XAA-Idb-sb.png (file)EdS8 KB (Removed unnecessary collection of diagramming elements)2
17:24, 8 January 2011Rdy-sync-no-via-6502d-jssim.png (file)EdS47 KB (image of JSSim view of 6502D layout showing RDY and SYNC cross with a poly landing pad but are not via-connected.)1
17:22, 8 January 2011Rdy-sync-no-via-R6502-balazs.png (file)EdS223 KB (closeup of Balazs' R6502 photo showing RDY and SYNC cross with a poly landing pad but are not via-connected.)1
17:21, 8 January 2011Rdy-sync-no-via-2A03.png (file)EdS110 KB (closeup of 2A03 photo showing RDY and SYNC cross with a poly landing pad but are not via-connected.)1
16:06, 8 January 2011Compare-r6502-balazs-2a03-dbe-short.png (file)EdS190 KB (Composite of the corresponding areas on 3 chips showing DBE (data bus enable) is shorted to cclk (on-chip version of phi2) only on Rockwell R6502)1
13:50, 5 January 20116502_photo_wrong-clock.jpg (file)EdS44 KB (Close up of R6502 layout showing datapath control lines clocked oddly with missing vias)1
11:16, 18 December 2010ARM1_promo_large.jpg (file)EdS5.09 MB (Original ARM1 (1985, 3micron) image scanned from Acorn's R140 promotional brochure, copyright now ARM Holdings Limited. Uploaded with the assistance and by kind permission of ARM.)1
11:10, 18 December 2010ARM1-LeeSmith.jpg (file)EdS370 KB (From Lee Smith's presentation "A Brief History of ARM", slide titled "First ARM Silicon: 26th April 1985" Image originally from Acorn promotional materials, copyright now ARM Holdings Limited. Uploaded by kind permission of ARM.)1
08:40, 10 December 201068000_vec_annot.jpg (file)Visual6502764 KB 1
06:15, 1 October 20106507_20x_top-000008r.jpg (file)V6wiki253 KB 1
06:14, 1 October 20106507_20x_top-000007r.jpg (file)V6wiki754 KB 1
06:14, 1 October 20106507_20x_top-000004r.jpg (file)V6wiki240 KB 1
06:14, 1 October 20106507_20x_top-000003r.jpg (file)V6wiki396 KB 1
06:13, 1 October 20106507_20x_top-000000r.jpg (file)V6wiki519 KB 1
18:29, 29 September 2010Stack_reg_high2_SPVTB.jpg (file)Visual6502256 KB 1
18:28, 29 September 2010Stack_reg_high2_subTied.jpg (file)Visual6502369 KB 1
18:28, 29 September 2010Stack_reg_high2_vec.jpg (file)Visual6502256 KB 1
18:28, 29 September 2010Stack_reg_high2_sub.jpg (file)Visual6502209 KB 1
18:27, 29 September 2010Stack_reg_high2_top.jpg (file)Visual6502395 KB 1

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